Technical Field
The present application relates to circuits. More specifically, the present application relates to a method for verifying the functionality of a digital circuit.
Description of the Prior Art
In clocked systems, skew might occur when sequences of parallel data packets transmitted along parallel data transfer paths lose time reference due to different data transfer path lengths and data transfer path impedances of the data transfer paths. These systems may not function properly if the skew is not corrected by deskew circuits (i.e., circuits dedicated to the deskewing of signals transmitted along parallel data transfer paths). Typically, a deskew circuit of the sender simultaneously inserts identical control data packets in data sequences transmitted along all the parallel data transfer paths, and a deskew circuit of the receiver buffers the transmitted data sequence and erases some or all of the control data packets inserted by the deskew circuit of the sender so that the data following directly the inserted control data packets is forwarded by the deskew circuit of the receiver roughly at the same time for all data transfer paths. Exemplary systems comprising deskew circuits are disclosed in WO 2013/176954, US 2013/0283085, U.S. Pat. No. 8,526,554, US 2011/0243211, U.S. Pat. No. 7,979,608, U.S. Pat. No. 7,197,100, U.S. Pat. No. 7,500,131, and US 2012/0030438, wherein some of these systems specifically refer to the widely spread PCIe networks. In PCIe networks, the parallel data transfer paths consist of lanes composed of two differential signaling pairs. One pair is for receiving data and the other pair is for sending data.
In general, the verification of the proper operation of the deskew circuits is as critical as the verification of the further operation of the systems comprising the deskew circuits. However, the deskew circuits perform the deskew mechanisms to be verified only if there is actually skew. In contrast to other simulations, it is not sufficient to apply different test vectors (sets of input signals applied during the simulation) as the skew is an inherent feature of the data transfer paths. Currently, delay elements are inserted in the simulated circuits in order to verify different skew scenarios in simulations, wherein different delay elements are required for each skew scenario so that the verification of the deskew circuits is very time-consuming.